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New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
Designers increasingly use complex reset signaling architectures to meet high-performance, low-latency, and low-power requirements. Specifically, independent reset domains are created by complex reset sequences, reset circuitry, and the intermixing of IPs with different reset schemas, power-management domains, and security domains or functionality. This increase in reset signaling complexity is creating new RDC verification challenges that… New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
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GOMACTech 2024
Embassy Suites by Hilton Charleston Convention Center, Charleston, SC, United StatesGOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC, and provides a forum for… GOMACTech 2024
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Virtuoso – Save on Signoff Effort with In-Design DRC and Fill
Virtuoso Layout Suite has pioneered in-design DRC checking and fixing in the layout editor. However, many of you have realized that the lack of completeness of rules in the techfile has caused many violations to fall through the cracks and are discovered later during signoff. An in-design DRC checking with signoff rule decks often comes… Virtuoso – Save on Signoff Effort with In-Design DRC and Fill
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DVClub Europe: Latest VHDL Verification Techniques
This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM Agenda (GMT) 13:00 Welcome and Introduction – Mike Bartley, Tessolve 13:00 Epsen Tallaksen, EmLogic - Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage) 13:30 Jim Lewis, SynthWorks - OSVVM in a NutShell, VHDL’s #1 Verification Methodology 14:00 Close Additional… DVClub Europe: Latest VHDL Verification Techniques
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SNUG Silicon Valley 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesConnecting the Synopsys User Community SNUG conferences have connected Synopsys global users for more than three decades. SNUG 2024 will once again provide a place where users and technical experts can meet, network, and share ideas about chip and system design. Technical Committee SNUG thanks the members of the Technical Committee who volunteer their time… SNUG Silicon Valley 2024
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Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform
With the growing complexities of 3D-ICs, chiplets, advanced packaging, and high-performance boards, engineers need a unified solution that provides early insight and analysis to detect and correct design problems before it is too late. This solution must also offer the ability to simulate the entire design efficiently, providing confidence in system signoff. Join our webinar… Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform
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AI-Powered Electromagnetics Symposium
Cadence Design Systems, Building 5 2655 Seely Avenue, San Jose, CA, United StatesAccelerate Your Designs with Generative AI-Powered Multiphysics Analysis and Optimization How are you addressing the ever-increasing complexity and density of your high-performance electronic systems? What role do electromagnetic effects such as electromagnetic interference (EMI), electromagnetic compatibility (EMC), power integrity, and signal integrity play? Discover how Cadence is transforming electromagnetic (EM) simulation for optimal design performance with… AI-Powered Electromagnetics Symposium
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High-Performance RTL Simulation Workflow with Vivado and Active-HDL
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs).… High-Performance RTL Simulation Workflow with Vivado and Active-HDL
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Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can be a bottleneck in the project cycle due to its complexity. The nature of a GLS can cause simulations to run much longer than the… Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
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Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices
Learn How STMicroelectronics Silicon Carbide (SiC) Research Team uses Silvaco TCAD to Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices During SiC device switching operations, it is possible that devices could be reaching abnormal overload conditions, which is why some applications require “robustness” specifications (e.g., Short Circuit and UIS… Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices
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High-Performance RTL Simulation Workflow with Quartus and Active-HDL
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs).… High-Performance RTL Simulation Workflow with Quartus and Active-HDL
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RISC-V Instruction Set Architecture: Enhancing Computing Power
*Work email required for registration* Don't miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that promises to inspire and inform: - Gain insights into the latest trends shaping chip design. - Learn from industry leaders about the strategies behind successful… RISC-V Instruction Set Architecture: Enhancing Computing Power
12 events found.