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Cost effective 5G for the IoT
5G RedCap is an exciting new 3GPP feature, soon to be introduced in Rel. 17 of the standard, targeting reduced capability use cases for industrial, wearables, and IoT in general. We will discuss the new standard, the market potential, and CEVA’s new PentaG2-Lite comprehensive baseband modem solution. Join CEVA to learn about: Introduction to the… Cost effective 5G for the IoT
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Extending Processors into Flexible Accelerators for 5G
The slowing down of Moore’s law and Dennard scaling has triggered an increased interest in application-specific instruction set processors (ASIPs). ASIPs implement a specialized instruction set architecture (ISA) tailored to the application and can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the acceleration domain, and thus more flexibility and agility in both the… Extending Processors into Flexible Accelerators for 5G
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Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis
Today’s million gates integrated circuits (ICs) involve various intellectual properties (IPs) interfacing with each other through multiple asynchronous clock and reset domains. Ensuring all clocks propagate concurrently across each clock tree components used as clock switching elements or each sequential or combinatorial component, clock output of which becomes asynchronous with respect to the clock input… Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis
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Advances in OSVVM’s Verification Data Structures
OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously in this webinar series. This webinar focuses on advances in OSVVM data structures. OSVVM's Functional Coverage,… Advances in OSVVM’s Verification Data Structures
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Balancing analog layout parasitics in MOSFET differential pairs
We have another #Pulsic webinar coming soon! This time we are taking a good look into MOSFET differential pairs with Paul Clewes. In this webinar, Paul will look at how to achieve a carefully balanced differential pair layout and consider the layout effects that impact the performance of a differential pair. Along the way, Paul will demonstrate… Balancing analog layout parasitics in MOSFET differential pairs
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TSMC 2022 Technology Symposium – Israel
Daniel Herzliya Hotel Ramat Yam St 60, Herzliya, IsraelIsrael Technology Workshop (In-Person Event) Date June 28, 2022 (Tuesday) Time 9:30a.m. - 4:30p.m. Venue Daniel Herzliya Hotel Ramat Yam St 60, Herzliya, Israel Europe Technology Symposium (Online VOD Event) Date June 30, 2022 (Thursday) Website link to be announced in June Get the latest on: TSMC’s smartphone, HPC, IoT, and automotive platform solutions TSMC’s… TSMC 2022 Technology Symposium – Israel
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PIC International Conference
Sheraton Brussels Airport Hotel Brussels, BelgiumThe 6th PIC International conference will build on the success of its predecessors, with industry-leading insiders delivering more than 30 presentations spanning four sectors. Attendees at the two-day conference will gain an up-to-date overview of the status of the global photonics industry, and will have the opportunity to meet many other key players within the… PIC International Conference
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Develop and Verify Designs Using a Silicon Photonics Platform with Integrated Lasers
As the optical transceiver market moves from 400GBs to 800GBs, many complex analog components are required to assemble energy efficient and cost-effective optical modules. At this joint webinar we will use an 800G-DR8 PIC design case study to show how to accurately develop Photonic Integrated Circuit (PIC) designs with a focus on co-simulating and synthesizing… Develop and Verify Designs Using a Silicon Photonics Platform with Integrated Lasers
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SecuryzrTM iSSP: Simplifying security lifecycle management with PUF
A Physically Unclonable Function or PUF is a function used to generate secret information on-chip. Information such as a secret key / public key pair may be generated on-chip each time it is needed, while the secret key never needs to be output from the chip. Thus the attack surface is reduced, since only the… SecuryzrTM iSSP: Simplifying security lifecycle management with PUF
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Optimizing Fault Simulations with Formal Analysis to Achieve ASIL Compliance for Automotive Designs
Most safety critical SoCs, such as those developed for automotive driver aid systems, require ASIL-D compliance. ASIL-D is the highest grade in the ISO 26262 Standard’s risk classification system, required less than 1% Single Point Fault. According to the ISO 26262 Standard, fault campaign on the targeted designs is the recommended methodology to generate FMEDA… Optimizing Fault Simulations with Formal Analysis to Achieve ASIL Compliance for Automotive Designs
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TSMC 2022 Technology Symposium – China, Virtual
Date June 30, 2022 (Thursday) Time Starts at 9:00 a.m. Website link to be announced in June Get the latest on: TSMC's smartphone, HPC, IoT, and automotive platform solutions TSMC's advanced technology progress on 5nm, 4nm, 3nm processes and beyond TSMC's specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and… TSMC 2022 Technology Symposium – China, Virtual
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Silvaco Flow Helps Designing and Simulating Pixel Arrays in Flat Panel Displays and Detectors
Designers of flat panel displays and detectors often rely on a variety of point tools from different EDA vendors that make the design flow discontinuous and difficult to integrate. These challenges, together with specific advanced display technology requirements, are addressed by the seamless and unique Silvaco TCAD-EDA flow. This webinar highlights how leading display and… Silvaco Flow Helps Designing and Simulating Pixel Arrays in Flat Panel Displays and Detectors
12 events found.