Extending Processors into Flexible Accelerators for 5G

The slowing down of Moore’s law and Dennard scaling has triggered an increased interest in application-specific instruction set processors (ASIPs). ASIPs implement a specialized instruction set architecture (ISA) tailored to the application and can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the acceleration domain, and thus more flexibility and agility in both the design process and the end product.

Join us at Synopsys’ ASIP Designer™ Virtual Seminar 2022 to learn why ASIPs are getting so much attention these days, and why Synopsys’ ASIP Designer is the industry’s leading tool to design, implement, program and verify such specialized processors.
This event focuses on ASIPs for 5G wireless applications and will cover the following topics:

• An introduction to the ASIP Designer tool suite
• Case study: An Application Specific Vector Processor for CNN-based Massive MIMO Positioning
• Case study: 5G NR MMSE Channel Equalization using Cholesky Decomposition

If you are a design engineer, algorithm developer, software engineer, system architect, or design manager focusing on advanced SoCs requiring application-specific optimizations, you won’t want to miss this event.

Patrick Verbist is the Product Marketing Manager for Synopsys’ ASIP Designer tools. Previously he was Business Development Manager and Field Application Engineer for the ASIP Designer tools and, prior to the acquisition by Synopsys in 2014, Director of Sales at Target Compiler Technologies. Before Target, Patrick worked for 12 years as Business Development Manager for imec in Belgium and San Jose (US). He holds a Master’s degree in Electrical Engineering from KU Leuven, Belgium.

Falco Munsche is the Technical Marketing Manager for Synopsys’ ASIP Designer tools. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP design tools for Synopsys and CoWare, and as a Design Consultant for Synopsys. He holds a Ph.D. (2002) and Dipl-Ing. degree (1995) in Electrical Engineering from RWTH Aachen University.

Mohammad Attari is currently a PhD student in the Digital ASIC research group in the Electrical and Information Technology (EIT) department at Lund University. His research focuses on developing Massive MIMO and next generation baseband communications processors. His interests include (but are not limited to) computer architecture, domain specific architectures, accelerator-level parallelism, application specific instruction set processors (ASIP), neural networks, and cross-level hardware-software (-algorithm) codesign and implementation.