-
-
Methodics User Group
An event driven platform for managing the design lifecycle is considered the holy grail for many semiconductor enterprises. It can enable DevOps automation and optimize many of the manual processes that affect team productivity. Although some tools try to use triggers to track important metadata during the design process, Methodics IPLM is taking a different… Methodics User Group
-
Early and Accelerated SoC Connectivity Verification using VC Formal Connectivity Checking App
Complex bus protocols, increased on-chip functionalities, coupled with limited shared I/O resources, result in complex wiring connections in SoCs with numerous muxing schemes. Simulation and structural analysis approaches require huge effort and may lead to bug escapes making them inefficient for SoC connectivity verification. Connectivity verification using formal techniques is exhaustive and helps making… Early and Accelerated SoC Connectivity Verification using VC Formal Connectivity Checking App
-
CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles
System planning is a major part of multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do bump assignment and optimization along with 3D structures implementation. With methodology evolving for different types of designs, a top-down and… CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles
-
Spatial Audio: What it is and how to overcome its unique challenges to provide a complete solution
Audiovisual experiences in XR, gaming, movies, and concerts can all be enhanced with spatial audio experience immersive technology. A superior spatial audio experience occurs when you combine headphones, with wearable head tracking, and on-device processing. Believe it or not, despite the recent wide adoption of Spatial/3D Audio, the concept and technology have been around for a… Spatial Audio: What it is and how to overcome its unique challenges to provide a complete solution
-
Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator? • Do you need to size the AI accelerator for existing and future AI requirements? • Would it be beneficial if you knew the latency advantage between ARM, RISC, DSP and Accelerator in deploying AI tasks? This webinar… Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
-
How to Optimize and Boost Your Device Modeling and Characterization with Utmost IV
In this webinar we will examine some of the key features and advantages of Utmost IV for device modeling and characterization, and the major design flows where Utmost IV is a key component. We will also present the latest product enhancements and introduce the new Utmost IV Corner and Retargeting Module. To conclude, we will… How to Optimize and Boost Your Device Modeling and Characterization with Utmost IV
-
Power Intent Management for Large SoCs
Defacto Techologie 2 rue Emile Augier, Grenoble, FranceThe complexity of system on chips keeps increasing and SoC designers keep having lot of pressure to deliver and keeping the cost as low as possible. To stay within a PPA budget (power performance area), it's challenging daily for designers. Defacto’s SoC Compiler keep providing innovative solutions to increase the productivity of designers. During this… Power Intent Management for Large SoCs
-
Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs
Requirements-based verification (RBV) is a popular verification process for FPGA designs used in safety-critical systems. The effectiveness of RBV is limited by the quality and precision of the requirements. Verification techniques such as constrained random verification with assertion-based verification (ABV) can be used to help identify ambiguous or incomplete requirements early in the design and… Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs
-
2021 ESD Alliance | IEEE CEDA Phil Kaufman Award
The GlassHouse 2 S Market Street, San Jose, CA, United StatesThe Electronic System Design Alliance and The IEEE Council on EDA (CEDA) are proud to honor DR. ANIRUDH DEVGAN President and CEO of Cadence Design Systems with the 2021 Phil Kaufman Award Dr. Devgan is being honored for his extensive contributions to electronic design automation (EDA). He is widely recognized as a leading authority in… 2021 ESD Alliance | IEEE CEDA Phil Kaufman Award
-
DATE 2022
Design, Automation and Test in Europe Conference | The European Event for Electronic System Design & Test DATE conference is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. DATE puts a… DATE 2022
-
Memory Bandwidth Races Higher with HBM3
With the formal release of the HBM3 specification, memory bandwidth for AI/ML and HPC shifts to a higher gear. Terabytes of bandwidth are possible using HBM3’s 2.5D/3D architecture. Join memory expert Frank Ferro as he discusses what changes come with the new generation of HBM, and how the Rambus HBM3 memory subsystem can help designers… Memory Bandwidth Races Higher with HBM3
-
Using ST Stellar MCU Virtual Prototypes to Deliver Next-Generation Software-Defined Vehicles
Automotive microcontrollers for next-generation software-defined vehicles need to deliver higher software capabilities. ST Stellar Integration MCUs offer safe, secure, and deterministic solutions for new vehicle architectures. The use of virtual prototypes is a key enabler to solving the emerging, complex software development challenges throughout the automotive design and test supply chain, such as feature integration,… Using ST Stellar MCU Virtual Prototypes to Deliver Next-Generation Software-Defined Vehicles
12 events found.