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CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles

March 9 @ 10:00 am - 11:00 am PST

Cadence, Multi-Chiplet

System planning is a major part of multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do bump assignment and optimization along with 3D structures implementation. With methodology evolving for different types of designs, a top-down and a bottom-up approach for implementation is possible.

In this session, learn about the different approaches to 3D partitioning, implementation, and unique capabilities available with Integrity 3D-IC platform for bump planning, interposer routing, and top-down 3D partitioning and implementation available with the Integrity 3D-IC platform.

Details

Date:
March 9
Time:
10:00 am - 11:00 am PST
Event Categories:
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Website:
Event Website

Organizer

Cadence
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