CDC
Pre-empt Late-stage Low Power Issues using Predictive Analysis
Low power is an increasingly critical requirement for all modern SoCs. Moreover, it is becoming more and more difficult with complex architectures being used in modern designs. This has made it necessary for designers to invest heavily in this verification effort throughout the design development cycle starting from architecture definition, RTL development, to final netlist tape-out. Conventionally, static low power flow constitutes defining and cleaning… Read More »Pre-empt Late-stage Low Power Issues using Predictive Analysis
Running CDC Analysis with Xilinx Parameterized Macros
Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks running at different frequencies, very often asynchronous to each other, and still be expected to work reliably. Xilinx Parameterized Macros (XPM) can be used to implement CDC, FIFO and BRAM… Read More »Running CDC Analysis with Xilinx Parameterized Macros
Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis
Today’s million gates integrated circuits (ICs) involve various intellectual properties (IPs) interfacing with each other through multiple asynchronous clock and reset domains. Ensuring all clocks propagate concurrently across each clock tree components used as clock switching elements or each sequential or combinatorial component, clock output of which becomes asynchronous with respect to the clock input… Read More »Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis
CDC Verification with Hard IP Blocks
Most FPGA designs contain configurable hard IP blocks supplied by FPGA vendors. These Hard IP blocks do not contain synthesizable RTL code, and therefore are excluded from advanced linting. In fact, this is a correct approach as hard IP blocks are assumed to be functionally stable and may be excluded from both static and dynamic… Read More »CDC Verification with Hard IP Blocks
Shorten Your CDC Debug Cycle by 10X with ML-based RCA
Over the last few decades System on Chip (SoC) design size has dramatically increased, and more complexity has been introduced to deliver the desired functionality. Growing design sizes lead to the introduction of several asynchronous clocks which can result in the reporting of millions of clock domain crossings (CDC) at the IP/SoC level. This leads… Read More »Shorten Your CDC Debug Cycle by 10X with ML-based RCA
Static Sign-Off Symposium 2023
DoubleTree Hotel 2050 Gateway Place, San Jose, CA, United StatesAdvanced Static Sign-Off Methodologies Leading SoC designers will share their advanced static sign-off methodologies and best practices to support first-silicon design goals, along with results achieved in accelerating early functional verification and sign-off of digital designs. Topics will include: AI/ML, targeted sign-off, incremental sign-off, multimode, hierarchical, dynamic CDC, and more. Advanced Static Sign-Off Methodology Presenters:… Read More »Static Sign-Off Symposium 2023
Comprehensive Static Verification for FPGA and ASIC RTL Designers
As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in the hands of RTL designers to eliminate bugs at their source. This webinar covers comprehensive static verification capabilities in the Cadence® Jasper™ Superlint and CDC apps for… Read More »Comprehensive Static Verification for FPGA and ASIC RTL Designers