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CDC Verification with Hard IP Blocks

September 8 @ 11:00 am - 12:00 pm PDT

Aldec, September 8, 2022

Most FPGA designs contain configurable hard IP blocks supplied by FPGA vendors. These Hard IP blocks do not contain synthesizable RTL code, and therefore are excluded from advanced linting. In fact, this is a correct approach as hard IP blocks are assumed to be functionally stable and may be excluded from both static and dynamic verification. However, clock domain crossing verification still requires hard IP block constraining. These block-level constraints serve the following purposes:

  • Identify clock and reset ports, as well as required reset polarity and synchronization
  • Identify required clock phases for I/O ports
  • Describe hard IP as one of valid CDC synchronizer circuits
During automated conversion of FPGA vendor projects, hard IPs were automatically constrained by the tool. These constraints are extracted from hard IP instance connectivity. In most cases, these IP-level constraints are not complete and require special attention from designers, as the top-level CDC analysis relies on the quality and completeness of hard IP constraints.
In this webinar, we will present a robust hard IP design constraints development methodology. This methodology is illustrated for different IP block types and on the number of FPGA designs.
Agenda:
  • Short CDC Analysis Overview
  • Aldec Design Constraints for block-level constraining
  • Constraining Single-Clock hard IP blocks
  • Constraining Multiple-Clock hard IP blocks
  • CDC Analysis of design with Hard IP blocks
  • Live Demo
  • Conclusion
  • Q&A
Webinar Duration:
  • 45 min presentation/live demo
  • 15 min Q&A

Bio:

Alexander Gnusin, Design Verification Technologist.
Alex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.

Details

Date:
September 8
Time:
11:00 am - 12:00 pm PDT
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Organizer

Aldec
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