Comprehensive Static Verification for FPGA and ASIC RTL Designers

As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in the hands of RTL designers to eliminate bugs at their source.

This webinar covers comprehensive static verification capabilities in the Cadence^® Jasper^™ Superlint and CDC apps for lint, design-for-test (DFT), clock domain crossing (CDC), and reset domain crossing (RDC).

What You Will Learn

• All the static checks that should be performed to hand off better-quality RTL
• How Jasper apps provide easy-to-use debug capabilities, leveraging Jasper’s industry-leading formal verification technology to reduce noise and automate violation handling and waivers
• Automatic formal checks, which do not require any formal verification experience, add significant value beyond the structural-only checks that most designers are used to

FPGA designs have grown immensely in complexity and are just as prone to CDC bug escapes as ASIC designs, so we encourage all RTL designers to attend.