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Running CDC Analysis with Xilinx Parameterized Macros

April 14 @ 11:00 am - 12:00 pm PDT

Aldec, April 14, 2022

Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks running at different frequencies, very often asynchronous to each other, and still be expected to work reliably.

Xilinx Parameterized Macros (XPM) can be used to implement CDC, FIFO and BRAM solutions in FPGA designs. XPM usage enables safe cross-clock domain transfers for control signals and data buses, providing seven clock domain crossing (CDC) capabilities such as single-bit, pulse, gray-code or handshake synchronizers.

Also, Xilinx Vivado provides a CDC checker, reporting paths that start in one clock domain and pass into another.  However, the capabilities of Vivado CDC checker are limited compared to advanced CDC analysis tools, while rigorous CDC verification is essential for safety and functional reliability of FPGA designs.

In this webinar, we will present the methodology and design examples of efficient CDC verification for designs containing Xilinx Parametric Macros.

Agenda:

  • Overview оf CDC Issues in FPGA designs
  • XPM overview:
    • XPM Usage for CDC transfers
    • XPM Functional Checks
  • XPM-based CDC Analysis with Vivado
  • XPM-based CDC Analysis with ALINT-PRO
    • Design Constraints Checks
    • Clock, Reset Trees verification
    • Enhanced CDC Analysis with XPM
  • CDC Functional Verification of XPM-based designs
  • Conclusion
  • Questions and Answers

Webinar Duration: 

  • 45 min presentation/live demo 
  • 15 min Q&A

Presenter Bio:

Alex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. His employees list includes IBM, Nortel, Ericsson and Synopsys Inc. As a verification prime for a multi-million gates project, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.

Details

Date:
April 14
Time:
11:00 am - 12:00 pm PDT
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Website:
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Organizer

Aldec
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