FinFET
Events
-
-
Managing the Complexity of FinFET Standard Cell Layout with Cello
FinFET technologies have enabled designs with increased density and performance while reducing power, when compared to MOSFET. However, this comes at a cost of increased design complexity. Not only are some undesirable layout dependent effects more pronounced, but design rules have become much more complex. Many design rules violations can no longer be fixed within… Managing the Complexity of FinFET Standard Cell Layout with Cello
-
-
Tackling Advanced Analog FinFET Front-End Design Challenges with Better Methodologies
Analog engineers adopting advanced FinFET technologies face many challenges that were not present when using planar transistors. Challenges in layout implementation have a direct impact on design specifications, and the luxury of over-margining is long gone. There are no third-order effects anymore, and managing layout effects, such as device and interconnect parasitics, variation, matching, and EM-IR,… Tackling Advanced Analog FinFET Front-End Design Challenges with Better Methodologies
-
Tackling Advanced Analog FinFET Back-End Design Challenges
The layout implementation of analog circuits in advanced FinFET technologies is becoming increasingly complex and challenging, with many new design rules to consider and multi-patterning, density rules, matching, and EM-IR concerns. These challenges can translate to longer layout turnaround times and reduced productivity. Join this CadenceTECHTALK to learn about silicon-proven technologies that improve layout engineering… Tackling Advanced Analog FinFET Back-End Design Challenges
-
-
Learn How to Efficiently Achieve Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory Process
When employing process simulation to generate a complex device structure, TCAD engineers often face the task of reproducing the exact etch profile that has been observed in semiconductor fabrication. Silvaco Victory Process offers several geometric models to efficiently achieve etch geometries that accurately match microscopy images (e.g., transmission electron microscopy). In this webinar, we present… Learn How to Efficiently Achieve Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory Process