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Tackling Advanced Analog FinFET Back-End Design Challenges

May 12, 2022 @ 11:00 am - 12:00 pm PDT

Cadence, May 12, 2022

The layout implementation of analog circuits in advanced FinFET technologies is becoming increasingly complex and challenging, with many new design rules to consider and multi-patterning, density rules, matching, and EM-IR concerns. These challenges can translate to longer layout turnaround times and reduced productivity.

Join this CadenceTECHTALK to learn about silicon-proven technologies that improve layout engineering productivity and efficiency. It is ideal for layout designers and recommended for CAD and analog engineers.

Date and Time
North America
May 12, 2022
11:00am PDT / 2:00pm EDT

May 12, 2022
9:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST


May 12, 2022
11:00 am - 12:00 pm PDT
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