Formal
Verification Day 2021
This virtual event provides an opportunity to stay informed about the latest innovations, techniques and methodologies in verification hardware and software. This 2-day event will share experiences and insights from users solving tough verification challenges using Synopsys solutions. This year’s event will have a special focus on technology trends and case studies spanning simulation, static,… Read More »Verification Day 2021
Forum on Specification and Design Languages
LIT Open Innovation Center Altenberger Str. 69, Linz, AustriaFDL is a well-established international forum to exchange experiences and promote new trends in the application of languages, their associated design methods, and tools for the design of electronic systems. FDL stimulates scientific and controversial discussions within and in-between scientific topics as described below. The program structure includes research working sessions, embedded tutorials, panels, and… Read More »Forum on Specification and Design Languages
Microelectronics Design Security: Better with Formal Methods
Whether you are developing Systems-on-Chip (SoCs) for mobile and wearables, automotive, aerospace, defense, data centers, or entertainment, securing your proprietary data and customers’ information is critical to your company’s long-term success. Hackers can exploit vulnerabilities in these systems — at the network, system, device, or chip levels. As SoC designs get more complex, this 30-minute… Read More »Microelectronics Design Security: Better with Formal Methods