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Microelectronics Design Security: Better with Formal Methods

June 14, 2023 @ 1:00 pm - 2:00 pm EDT

Synopsys+SAE, June 14, 2023

Whether you are developing Systems-on-Chip (SoCs) for mobile and wearables, automotive, aerospace, defense, data centers, or entertainment, securing your proprietary data and customers’ information is critical to your company’s long-term success. Hackers can exploit vulnerabilities in these systems — at the network, system, device, or chip levels. As SoC designs get more complex, this 30-minute Webinar aims to show chip designers how they can best ensure secure data is handled correctly inside the chip while reducing deployment time.

This Webinar will help attendees understand:

  • The role of formal methods for security verification
  • The key challenges of formal verification and why addressing them is critical
  • How to ensure information flow tracking verifies data integrity and leakage issues
  • How a next-generation formal verification solution is helping users analyze and debug the root cause of security violations

An audience Q&A session will follow the technical presentation.

Jin Zhang is a Director of Product Management at Synopsys, who is responsible for VC Formal. Jin has more than 25 years of experience working in the EDA industry, driving new products and technologies to the market in the formal verification space. She worked at Cadence, Real Intent, EVE, and Oski Technology prior to joining Synopsys. Jin holds a Ph.D. in electrical and computer engineering and an MBA in international management.
Ian Land serves as Synopsys’s Senior Director of Security, Government, and Aerospace Solutions. Ian has more than 20 years of semiconductor experience and has spent more than 15 years in disciplines that require security. Before joining Synopsys, he worked for Intel, Altera, and Xilinx. Ian holds a bachelor’s degree in mechanical engineering from UCLA and a master’s degree in mechanical engineering and management from MIT.


June 14, 2023
1:00 pm - 2:00 pm EDT
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