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How to Reduce Thousands of False Errors in 15 Minutes
Analyzing electrical errors across an IP or a SoC at top level, can be a painful and long process, often requiring extensive setup time and hundred of hours to distinguish…
RISC-V Instruction Set Architecture: Enhancing Computing Power
*Work email required for registration* Don't miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that…
Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints. Clock domain crossing (CDC) challenges faced by design…