SemiWiki
PCIe 6.0 From IP to Interconnect in High-Performance Computing
ABSTRACT: PCI Express (PCIe) is one of the most popular interface technologies in the world. Interconnects for high-performance computing (HPC) in the data center, cloud and AI edge continue to increase in speed and density. System architects, SoC designers, PCB developers and SI engineers are challenged as never before to implement bleeding edge solutions. In… Read More »PCIe 6.0 From IP to Interconnect in High-Performance Computing
DVCon U.S. 2023
DoubleTree Hotel 2050 Gateway Place, San Jose, CA, United StatesThe 2023 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative, announces its call for extended abstract proposals. The submission site for extended abstracts will be open from July 11 through August 8, 2022. DVCon U.S. 2023 will be held February 27-March 2, 2023, at the Doubletree Hotel in San Jose, California.… Read More »DVCon U.S. 2023
PG Pcells- A Correct by Construction Power and Ground Distribution Strategy
Proper Power Strategy for Layouts comes with several requisites that pose great difficulty and are hard to balance without compromising on one or more aspects. Power strategy adds difficulty to an already complex process of floor-planning and is a time and labour-intensive implementation. It poses many challenges like hard to meet EM/IR specifications for a… Read More »PG Pcells- A Correct by Construction Power and Ground Distribution Strategy
Maximizing yields through collaboration
Semiconductor companies have long recognized the importance of yield management and having the right support in place to maximize results. In this 30-minute webinar brought to you by yieldHUB and SemiWiki, attendees will learn about a key to success in the world of yield management (and something that can be underestimated) - collaboration. This is… Read More »Maximizing yields through collaboration
Enhance Productivity with Machine Learning in the Analog Front-End Design Flow
Advanced semiconductor nanometer technology nodes, together with smart IC design applications enable today very complex and powerful systems for communication, automotive, data transmission, AI, IoT, medical, industry, energy harvesting, and many more. However, more aggressive time-to-market and higher performance requirements force IC designers to look for advanced and seamless design flows, tools & methodologies to… Read More »Enhance Productivity with Machine Learning in the Analog Front-End Design Flow
The ROI of User Experience Design: Increase Sales and Minimize Costs
In today's competitive landscape for IoT, edge, and cloud solutions, User Experience (UX) design has become more crucial than ever in achieving customer and business goals. During this live webinar, we will explore how UX design affects everything from sales, customer retention, time-to-market, to internal support and development costs. We'll delve into key principles of… Read More »The ROI of User Experience Design: Increase Sales and Minimize Costs
Design and Analysis of Multi-Die & 3D-IC Systems
The architecture and heterogeneous integration capability of 3D-IC (three-dimensional integrated circuits) offer many benefits. The latest configuration methods, CoWoS (Chip On Wafer on Substrate) and WoW (Wafer on Wafer) from TSMC, provide advantages by significantly reducing the interconnect length and signal power loss. These new technologies have introduced the need for innovative ways to solve… Read More »Design and Analysis of Multi-Die & 3D-IC Systems
An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development
This webinar explores front-end automation advances that encompass an innovative register information management system to capture hardware functionality and addressable register map in a single "executable" specification. Appropriate Audience: ● Architects/RTL Designers ● Verification Engineers ● Pre-Silicon Validation Teams ● Post-Silicon Lab Bring-up Team Members ● Technical Writers ● Firmware Engineers ● Embedded Programmers Learn… Read More »An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development
Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
As semiconductor industry leaders, Bosch, Infineon, Nordic Semiconductor, NXP, and Qualcomm collaborate to drive the acceleration of automotive RISC-V semiconductors, join us for an insightful webinar on how you too can unlock the full potential of RISC-V within your automotive SoC. Featuring Andes Technology and Green Hills Software, this webinar will offer key insights into… Read More »Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints. Clock domain crossing (CDC) challenges faced by design engineers include: - Speed and power requirements lead to designs with multiple asynchronous clock domains on different I/O interfaces and data being transferred from one… Read More »Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
RISC-V Instruction Set Architecture: Enhancing Computing Power
*Work email required for registration* Don't miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that promises to inspire and inform: - Gain insights into the latest trends shaping chip design. - Learn from industry leaders about the strategies behind successful… Read More »RISC-V Instruction Set Architecture: Enhancing Computing Power