Synopsys
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ICCAD 2023
Hyatt Regency San Francisco Downtown SoMa 50 3rd Street, San Francisco, CA, United StatesJointly sponsored by IEEE and ACM, ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technologies in the electronic design automation research areas. ICCAD covers the full range of CAD topics – from device and circuit level up through system level, as well as post-CMOS design. ICCAD has… ICCAD 2023
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RISC-V in Space
Omni Interlocken Hotel 5000 Interlocken boulevard, Broomfield, CO, United StatesJoin us for "RISC-V in... Space" on November 2, 2023, as we explore the exciting intersection of RISC-V, electronics design, and space! Agenda 9:30 AM - 10:00 AM Registration & Welcome 10:00 AM - 12:00 PM Case Study Presentations: Tenstorrent, Synopsys, RISC AI, Arteris IP 12:00 PM - 1:00 PM Lunch Buffet 1:00 PM - 3:00 PM Case Study Presentations: Breker Systems, Imperas,… RISC-V in Space
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IESA AI Summit
Trident Hotel Hyderabad Hyderabad, IndiaExperience the unprecedented growth opportunities in the semiconductor and electronics industry, fueled by rapid advancements in Artificial Intelligence (AI). Embrace the paradigm shift from software-centric approaches to hardware-centric solutions, captivating emerging markets in the realm of AI. Witness the powerful convergence of breakthrough technologies like the Internet of Things (IoT) and AI, igniting a renaissance… IESA AI Summit
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CMOS Circuit Techniques for Wireline Transmitters Part I
Synopsys Webinar – Part I In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume. This volume of network traffic demands an increase… CMOS Circuit Techniques for Wireline Transmitters Part I
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Tackling Challenges in 3D Heterogenous Integrated (3DHI) Microelectronics for Aerospace, Government, and Defense Systems
Join industry experts from aerospace, government, and defense as they discuss the complexities of 3D Heterogeneous Integration (3DHI), highlighting some of the technological, manufacturing, and economic complexities as well as security, reliability, and safety challenges. The panelists will also share their insights on chiplets and interface compatibility in addition to how DARPA’s NGMM (Next-Generation Microelectronics Manufacturing research… Tackling Challenges in 3D Heterogenous Integrated (3DHI) Microelectronics for Aerospace, Government, and Defense Systems
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ISTFA 2023
Phoenix Convention Center 100 North Third Street, Phoenix, AZ, United StatesSaving global resources by increasing energy efficiency is among the most significant problems that global society must address today. To achieve this, a major target is developing efficient and reliable power electronics devices for providing the required high-performing hardware components. Power semiconductors based on silicon carbide (SiC) and gallium nitride (GaN) technologies are becoming increasingly… ISTFA 2023
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DVCon Europe 2023
Holiday Inn Munich - City Centre Hochstraße 3, Munich, GermanyThe Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier European technical conference on system, software, design, verification, validation and integration. It is a place where the latest methodologies and technologies of tools, languages, and standards for integrated and embedded systems and products are shared and discussed. Applications of interest include (but… DVCon Europe 2023
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Automated Constraints Promotion Methodology from IP to SoC for Complex Designs
IP cores require integration into top-level subsystems and/or SoCs. Writing constraints manually for top level design is prone to errors and difficult to verify and manage. This Synopsys webinar will cover how automated SDC constraints promotion from the IP to SoC level provides high-quality SDC using Synopsys Timing Constraints Manager relative to manual time-consuming approaches. We will… Automated Constraints Promotion Methodology from IP to SoC for Complex Designs
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ASIP University Day 2023
ASIP University Day: Domain-Specific Processor Design using ASIP Designer Application-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs, i.e. when standard processor IP cannot meet challenging application-specific requirements, and fixed hardware is not flexible enough. Heterogeneous multicore systems including ASIPs are now becoming more mainstream. Domains such as… ASIP University Day 2023
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SystemC Evolution Day 2023
Holiday Inn Munich - City Centre Hochstraße 3, Munich, GermanyWorkshop on the Evolution of SystemC Standards: 16 November 2023 The eight SystemC Evolution Day is a full-day, technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. In several in-depth sessions, selected current and future standardization topics around SystemC will be discussed in order to accelerate their progress for inclusion in… SystemC Evolution Day 2023
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Making the Right Connections – Taking the Guess Work out of DFT Connectivity Validation
System-on-Chip (SoC) designs continue to grow in both size and complexity in order to meet the ever-growing performance and power demands associated with modern technology. To keep up with this fast-paced evolution, the corresponding design-for-test (DFT) logic required for manufacturing tests has also become more complex. Increasing transistor density, combined with a growing mix of… Making the Right Connections – Taking the Guess Work out of DFT Connectivity Validation
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CMOS Circuit Techniques for Wireline Transmitters Part II
Synopsys Webinar – Part II In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume. This volume of network traffic demands an increase… CMOS Circuit Techniques for Wireline Transmitters Part II