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VisualSim Architect
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Mapping SysML to hardware architecture
In this webinar, we will show how the SysML behavior models of a RADAR application can be mapped to a architecture model to measure the latency, throughput, power consumption, scheduling… Mapping SysML to hardware architecture
Evaluating UCIe based multi-die architectures to meet timing and power constraints
Multi-die architectures have evolved from proprietary to industry standard UCIe. UCIe can accommodate the bulk of designs today from 8 Gbps per pin to 32 Gbps per pin for high-bandwidth… Evaluating UCIe based multi-die architectures to meet timing and power constraints