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Mapping SysML to hardware architecture
March 21 @ 9:00 am - 10:00 am PDT
In this webinar, we will show how the SysML behavior models of a RADAR application can be mapped to a architecture model to measure the latency, throughput, power consumption, scheduling quality and response to bottleneck conditions. The application can be quickly mapped onto different architectures to meet the project requirements. This will enable better tuning of the application and respond to the needs of new projects.
For this Webinar, we will be using discrete-event, library-based graphical architecture exploration using VisualSim Architect. VisualSim is a modeling and simulation platform with a large library of modeling IP for networks, hardware, software, RTOS, traffic, statistics and analysis. The AI-based diagnostics engine accepts Requirements as input and continuously monitors the system for compliance.
This new approach facilities communication with the development team, providing better information to the MatLab algorithm team, feasibility studies and, faster proposal creation.