The recent surge in demand for mobile, networking, edge computing and automotive chips has challenged engineers to innovate across multiple domains – power efficiency, footprint… Read More »Synopsys: AMS SIG India – 10th Edition
Learn how to write UVM testbenches for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes to build reusable and scalable… Read More »Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification
When verifying large SoC designs, one needs to write SystemVerilog models for analog/mixed-signal blocks to comply with the digital verification flow, such as UVM. This… Read More »Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example
Send me your annual Holiday and New Years greetings, we could use some cheer during the pandemic, that’s for sure. 2019 2018 2017 2016 Team… Read More »Merry Christmas 2020