Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example

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When verifying large SoC designs, one needs to write SystemVerilog models for analog/mixed-signal blocks to comply with the digital verification flow, such as UVM. This talk addresses ways to extract those models automatically from circuits. The first approach is called … Continued

Merry Christmas 2020

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Send me your annual Holiday and New Years greetings, we could use some cheer during the pandemic, that’s for sure. 2019 2018 2017 2016 Team Maven Silicon wishes you and your family a Merry Christmas. #christmas #happychristmas #christmas2020 #festive #mavensilicon … Continued