The problem of optimization is a long-standing one in the field of design. For years, the most conventional approach was the brute-force method of running parametric sweeps on the design space. However, as systems become…
STAC Summits bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational intelligence to discuss important technical challenges in trading and investment.
Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard verification flows. Built on a SystemVerilog Real Number Modeling (RNM)…
IMS will be presented in-person, 11-16 June 2023 in San Diego, CA. IMS is the flagship event in a week dedicated to all things microwaves and RF. The week also includes the IEEE MTT-S Radio Frequency…
Theme Artificial Intelligence, Machine Learning, and Deep Learning: Tactical and Strategic Impacts to Microelectronics Design and Test About MDTS 2023 The IEEE Microelectronics Design & Test Symposium (MDTS) provides a forum for academic and industry…
With design boundaries constantly stretched and redefined, traditional borders for “custom design” no longer hold. Creative and intelligent solutions are imperative for boosting overall design, simulation, layout, and verification productivity through ever-changing specifications. Join us…
With the test technology facing its grand challenges to ensure the quality of ICs and electronic systems, incorporating more and more sophisticated manufacturing processes and system integration technologies in various emerging applications such as Internet…
The combined AI Hardware & Edge AI Summit comprehensively covers the design and deployment of ML hardware and software infrastructure across the cloud-edge continuum. For Enterprise ML Experts: Attend a unique AI systems event that will…
Join us at this webinar to learn more about the Cadence® EMX® Designer, our newly introduced passive component synthesis and optimization solution. In split seconds, the EMX Designer generates very flexible DRC-clean parametric cells of…
IC package design teams and characterization teams have had a “throw-it-over-the-wall” relationship for decades, which often delays design releases by months. However, as signal integrity (SI) and power integrity (PI) challenges evolve with multi-die heterogeneous…