Jasper User Group 2021

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It’s time for our annual formal verification user group CadenceCONNECT: Jasper User Group 2021. This in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification practices based on Cadence® JasperGold® formal verification … Continued

DVCon Europe 2021

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The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon … Continued

Addressing Growing Security Challenges with JasperGold

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Join Cadence® Training and Product Engineering Architect Joerg Mueller and Senior Application Engineer Tom Weiss for this free technical training webinar. As a chip designer, you’re probably spending as much headspace on security threats as you are on traditional challenges … Continued

How to Improve Your Chip Design Performance and Productivity Using Machine Learning

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New applications and technology are driving demand for even more compute power and functionality in the devices we use every day. This has resulted in the semiconductor industry experiencing strong growth based on technology like 5G, autonomous driving, hyperscale compute, … Continued

Benefits of a Common Methodology for Emulation and Prototyping

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Overview Many design teams have used some form of hardware verification throughout their verification cycle for years now. Some engineering teams prefer to use emulation, some prefer to use prototyping, and some even use both. Why would engineering teams invest … Continued

AI Hardware Summit

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AI Hardware is evolving – and so are we! As machine learning models continue to grow in size and complexity, and more and more models enter production in enterprises worldwide, the way we approach accelerating these workloads is changing. At … Continued

Cadence TECHTALK: Mixed-Signal SoC Verification Simplified with Xcelium Simulator (NA)

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Analog and mixed-signal verification has always been a challenge for design and verification engineers. It has become tedious with the increasing complexity of SoC designs. Join this webinar to learn how Cadence is providing effective verification and debug methodologies using … Continued

DVClub Europe

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Agenda (BST): Time Session Description           Slides              Videos 12.00 BST 16:30 IST Welcome and Introduction Mike Bartley, Senior Vice President – VLSI Design, Tessolve 12.05 BST 16:35 IST I’m Excited … Continued

Blog Updates for 2021

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We’re already into the new year, so it was about time that I updated my list of Semi and EDA vendors that I’ve blogged or consulted for, here’s what changed: Mentor became Siemens EDA Moortec acquired by Synopsys Methodics acquired … Continued

Merry Christmas 2020

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Send me your annual Holiday and New Years greetings, we could use some cheer during the pandemic, that’s for sure. 2019 2018 2017 2016 Team Maven Silicon wishes you and your family a Merry Christmas. #christmas #happychristmas #christmas2020 #festive #mavensilicon … Continued