The 6th PIC International conference will build on the success of its predecessors, with industry-leading insiders delivering more than 30 presentations spanning four sectors. Attendees at the two-day conference will gain an up-to-date overview of… PIC International Conference
System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped and rotated ICs may accidentally… Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
The Peripheral Component Interconnect Express (PCIe®) high-speed interface has become the standard for computer expansion cards due to its high bandwidth combined with manageable component costs. However, the latest PCIe 6.0 release raises new challenges… Conquer SI/PI Challenges and Reduce Time to Signoff for PCIe 6.0
The IEEE European Test Symposium (ETS) is Europe’s premier forum dedicated to presenting and discussing scientific results, emerging ideas, applications, hot topics and new trends in the area of electronic-based circuits and system testing, reliability,… European Test Symposium 2022
The premier event for practical, deployable computer vision and visual AI, for product creators who want to bring visual intelligence to products. The Summit attracts a global audience of technology professionals from companies developing computer… Embedded Vision Summit
ChipEx2022 The main event of the Israeli semiconductor industry, will be held on May 10, 2022 at the Expo Tel Aviv Conference Center. The event is expected to attract thousands of industry professionals including engineers, development managers, project… ChipEx 2022
Learn how to formally verify your design by automatically generating SystemVerilog Assertions (SVA) for your block-level register specifications, chip-level RTL, and RTL connectivity at the SoC level using ARV-Formal™.
We can’t wait to bring our community back together at the Michigan Science Center in Detroit. Join us 10-12 May to hear from over 50 speakers from companies across the autonomous vehicle perception supply chain,… AutoSense Detroit 2022
How do you deal with design requirements that span high performance, energy-efficient computing, and high-reliability implementation? To realize these goals, you need optimal design flows to deliver the best power, performance, and reliability. Join Cadence… Arm and Cadence: Achieving Best Silicon Power, Performance, and Area
The layout implementation of analog circuits in advanced FinFET technologies is becoming increasingly complex and challenging, with many new design rules to consider and multi-patterning, density rules, matching, and EM-IR concerns. These challenges can translate… Tackling Advanced Analog FinFET Back-End Design Challenges