The AXI4 Stream protocol is used as a standard interface to exchange data between connected IPs within FPGA designs. For crossing clock domains, the AXI4 Stream interconnect is based on switches capable of transferring data… Static and Dynamic CDC Verification of AXI4 Stream-based IPs
In 2021 Siemens EDA released CDC Assist. CDC Assist is an ML powered feature that empowers users to configure, debug, and close CDC on designs more rapidly. Following the success of CDC Assist, Siemens introduced… Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning
Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints. Clock domain crossing (CDC) challenges faced by design engineers include: – Speed and… Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in the hands of RTL designers… Comprehensive Static Verification for FPGA and ASIC RTL Designers
Over the last few decades System on Chip (SoC) design size has dramatically increased, and more complexity has been introduced to deliver the desired functionality. Growing design sizes lead to the introduction of several asynchronous… Shorten Your CDC Debug Cycle by 10X with ML-based RCA
Advanced Static Sign-Off Methodologies Leading SoC designers will share their advanced static sign-off methodologies and best practices to support first-silicon design goals, along with results achieved in accelerating early functional verification and sign-off of digital… Static Sign-Off Symposium 2023
Most FPGA designs contain configurable hard IP blocks supplied by FPGA vendors. These Hard IP blocks do not contain synthesizable RTL code, and therefore are excluded from advanced linting. In fact, this is a correct… CDC Verification with Hard IP Blocks
Today’s million gates integrated circuits (ICs) involve various intellectual properties (IPs) interfacing with each other through multiple asynchronous clock and reset domains. Ensuring all clocks propagate concurrently across each clock tree components used as clock… Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis
Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks running at different frequencies, very often asynchronous to each other,… Running CDC Analysis with Xilinx Parameterized Macros
Low power is an increasingly critical requirement for all modern SoCs. Moreover, it is becoming more and more difficult with complex architectures being used in modern designs. This has made it necessary for designers to invest heavily in this verification effort throughout… Pre-empt Late-stage Low Power Issues using Predictive Analysis