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Tessolve, 21 November 2024

FPGA Front Runner: FPGA Safety and Security

This event covers the challenges in ensuring an FPGA is secure and demonstrably safe as per the relevant industry safety standards. This includes supply chains, FPGA hardware and the IP used on the FPGA Agenda… FPGA Front Runner: FPGA Safety and Security

Tessolve, 24 September 2024

FPGA Front Runner: FPGA Verification Strategies

Time Speaker Details 09.30 Arrival and Registration 10.00 Dave Sanders, Rolls-Royce Overview of Rolls Royce @ Solihull Presentation Title – Rolls-Royce… the past, the present and the future Abstract – Rolls-Royce has come a long way since… FPGA Front Runner: FPGA Verification Strategies

Aldec, April 11, 2024

Making a Structured VHDL Testbench – A Demo for Beginners

Abstract: This demonstrated tutorial is intended for designers and verification engineers who want to learn to make better and more structured testbenches. This session will show you what is needed for any good testbench, irrespective… Making a Structured VHDL Testbench – A Demo for Beginners

FPGA Forum 2024

FPGA Forum 2024 – Norway

FPGA-forum is a yearly event for the Norwegian FPGA community. FPGA-designers, project managers, technical managers, researchers, final year students and the major vendors gather for a two-day focus on FPGA. There will be presentations from… FPGA Forum 2024 – Norway

FPGAworld 2023

FPGAworld Conference 2023 – Copenhagen

The FPGAworld Conference is an international forum for researchers, engineers, teachers, students, and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems, FPGA/ASIC-based products, educational & industrial cases, and more. Registration for attendees… FPGAworld Conference 2023 – Copenhagen

Aldec, August 31, 2023

Advanced Testbench for a Complex DUT

Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a… Advanced Testbench for a Complex DUT

Aldec, June 1, 2023

Advanced Testbench for a Simple DUT

Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a… Advanced Testbench for a Simple DUT

Verification Futures 2023 UK

Verification Futures 2023 UK

The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for… Verification Futures 2023 UK

FPGA Europe 2023

FPGA Conference Europe 2023

FPGAs have made a regular evolutional leap forward in terms of new approaches and solutions for both hardware- and software developers. The FPGA Conference Europe, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2, is… FPGA Conference Europe 2023

Aldec, May 5, 2022

FPGA Verification Architecture Optimization with UVVM

Presenter: Espen Tallaksen, CEO of EmLogic Thursday, May 5, 2022 Abstract: For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification… FPGA Verification Architecture Optimization with UVVM