Verification Futures 2023 UK
June 22 @ 8:00 am - 5:00 pm BST
The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally, we welcome students to encourage them on their first step into semiconductors as verification engineers.
| 08:30 | Arrival: Breakfast and Networking | ||||
| 09:25 | Welcome: Mike Bartley, Tessolve Semiconductor Ltd | ||||
| 09:30 | Functional safety for the world of Autonomous and Zonal. Madhusudan Rao, ARM Ltd |
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| 10:15 | How to build the future verification engineers? Francois Cerisier (AEDVICES) |
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| 10:30 | Application of AI in IC Design and Verification Matt Graham (Cadence Design Systems) |
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| 11:00 | Refreshments and Networking | ||||
| 11:30 | User presentations on Formal Verification | Student Session 1 | VHDL Verification | ||
| 11:30 | The Power of Formal Verification: From flops to billion-gate designs
Dr Ashish Darbari (Axiomise) |
Introduction to Verification and SystemVerilog for Beginners Dr David Long (Doulos) |
Speed up VHDL verification significantly by making a better testbench architecture and a simpler test sequencer. Espen Tallaksen (EmLogic) |
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| 11:50 | Automatic Software Formal Verification Nick Tudor (D-RisQ Ltd) |
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| 12:10 | Formally Verified High-Level Synthesis Yann Herklotz Grave (Imperial College) |
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| 12:30 | Lunch and Networking | ||||
| 13:30 | How does ChatGPT change ML in EDA Landscape? Ramesh Narayanaswamy (Synopsys Inc) |
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| 14:00 | Verification, bring-up, production – the wholly trinity Yiannis Nikolaou (Jump Trading International Ltd. ) |
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| 14:20 | RISC-V verification and implications of the 5:1 ratio of DV to design engineers Simon Davidmann (Imperas Software) |
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| 14:40 | Formal Verification in Practice Dr. Tobias Ludwig (Lubis EDA) |
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| 15:00 | Refreshments and Networking | ||||
| 15:30 | Latest topics in Verification | Student Session 2 | VHDL Verification | UVM for AMS Verification | |
| 15:30 | Verification Makeover with RISC-V Processor Designs Lavanya Jagan (Vyoma Systems Private Ltd) |
Is it easy to get started with UVM, or should I use Formal instead? Dr David Long (Doulos) |
Faster than “Lite” Verification Component Development with OSVVM Jim Lewis (SynthWorks Design Inc) |
Renesas’s Submission to the UVM-(A)MS working group
Peter Grove |
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| 15:50 | User experiences with open-source mainstream verification techniques Srinivasan Venkataramanan, Deepa Palaniappan (AsFigo Technologies) |
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| 16:10 | Closing Functional Coverage on A Compression Encoder with Deep Reinforcement Learning Eric Ohana, The University of Bielefeld, Germany |
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| 16:30 | Event Closes | ||||