Advanced Testbench for a Simple DUT
June 1 @ 11:00 am - 12:00 pm PDT
Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces.
In part 2 of this webinar series, we will show you how to verify a relatively simple DUT with high quality requirements using an advanced testbench without using any verification framework. We will also discuss the elements of an advanced testbench infrastructure to verify our simple DUT more efficiently, check and prove that we have indeed verified our simple DUT more thoroughly, start to use advanced Bus Functional Models (BFMs) that allow simpler and more advanced interface control, and introduce functional coverage.
Having shown you these more advanced testbench techniques, we will continue to show how UVVM can be used to implement them in the simplest ways possible and with a focus on readability, maintainability, and extensibility.
What is required when verifying for higher quality?
The elements of an advanced testbench infrastructure
BFM vs Protocol Checkers
Specification Coverage, aka Requirements Coverage
Introducing functional coverage
UVVM advanced BFMs
UVVM for high quality verification
45 min presentation/live demo
15 min Q&A
Simon Southwell has 35 years in Research and Development, with experience in ASIC design, FPGA, and embedded software development.
Espen Tallaksen, CEO of EmLogic
Espen is also the author and architect of UVVM and founder of previous Bitvis.
He has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.