FPGA

Aldec Oct 14

The most error prone FPGA corner cases

Presenter: Espen Tallaksen, CEO of EmLogic Thursday, October 14, 2021 Abstract: Cycle related corner cases are probably the worst and main reason for undetected bugs… Read More »The most error prone FPGA corner cases

Aldec UVM part 4

UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates

Abstract: Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2.  As with… Read More »UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates

Aldec Sept 16

UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM

Abstract: Today’s FPGAs have become larger in logic density and can handle complex designs with multi-million system logic cells. The traditional verification techniques of simple… Read More »UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM