TechNES FPGA Front Runner Event
The FPGA Front Runners event will be hosted by Renishaw at their venue in Wotton-under-Edge. The event will focus on “Using AI in development and… Read More »TechNES FPGA Front Runner Event
FPGA
High-Performance RTL Simulation Workflow with Libero and Active-HDL
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR)… Read More »High-Performance RTL Simulation Workflow with Libero and Active-HDL
High-Performance RTL Simulation Workflow with Quartus and Active-HDL
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR)… Read More »High-Performance RTL Simulation Workflow with Quartus and Active-HDL
High-Performance RTL Simulation Workflow with Vivado and Active-HDL
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR)… Read More »High-Performance RTL Simulation Workflow with Vivado and Active-HDL
FPGA Forum 2024 – Norway
FPGA-forum is a yearly event for the Norwegian FPGA community. FPGA-designers, project managers, technical managers, researchers, final year students and the major vendors gather for… Read More »FPGA Forum 2024 – Norway
FPGA Frontrunner Meet & Greet
The FPGA Front Runners event will be hosted by Thales at their venue in Reading. The event will focus on “Security at System Level, and… Read More »FPGA Frontrunner Meet & Greet
CHIPS Alliance – FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development
IP share and reuse is fundamental for efficient chip design. But in order to do this efficiently we need tools and methods. On the software… Read More »CHIPS Alliance – FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development
High Reliability and Functional Safety Applications for FPGA
When designing any new system, safety and reliability are key factors in determining if a system is safe for real-world deployment and if there are… Read More »High Reliability and Functional Safety Applications for FPGA
Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints
In this Webinar, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms… Read More »Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints
Maximize Design Productivity using Vivado ML with SystemVerilog
Although SystemVerilog is perhaps most widely used in the context of hardware verification, it also contains many features directly relevant to FPGA hardware designers. We… Read More »Maximize Design Productivity using Vivado ML with SystemVerilog