Latch-Up 2023
The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon to be held over the weekend of Friday, March 31… Read More »Latch-Up 2023
FPGA
CDC Verification with Hard IP Blocks
Most FPGA designs contain configurable hard IP blocks supplied by FPGA vendors. These Hard IP blocks do not contain synthesizable RTL code, and therefore are… Read More »CDC Verification with Hard IP Blocks
FPGAs for AI and AI for FPGAs
Artificial Intelligence (especially Deep Learning) is rapidly becoming the cornerstone of numerous applications, creating an ever-increasing demand for efficient Deep Learning (DL) processing. FPGAs provide… Read More »FPGAs for AI and AI for FPGAs
Advances in OSVVM’s Verification Data Structures
OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and… Read More »Advances in OSVVM’s Verification Data Structures
OSVVM’s Test Reports and Simulator Independent Scripting
According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify… Read More »OSVVM’s Test Reports and Simulator Independent Scripting
FPGA World 2022 – Copenhagen
The FPGAworld Conference is an international forum for researchers, engineers, teachers, students, and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems, FPGA/ASIC-based… Read More »FPGA World 2022 – Copenhagen
FPGA World 2022 – Stockholm
The FPGAworld Conference is an international forum for researchers, engineers, teachers, students, and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems, FPGA/ASIC-based… Read More »FPGA World 2022 – Stockholm
Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or… Read More »Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
FPGA Design/Verification: Code, Functional and Specification Coverage
Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you… Read More »FPGA Design/Verification: Code, Functional and Specification Coverage
Versal ACAP Workshop Online
The Xilinx Versal ACAP platform is multi-featured, offering unprecedented system level performance and integration. This informative workshop (delivered in 2 half day sessions) is a… Read More »Versal ACAP Workshop Online