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Aldec, April 4, 2024

High-Performance RTL Simulation Workflow with Libero and Active-HDL

Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will… High-Performance RTL Simulation Workflow with Libero and Active-HDL

Aldec, March 28, 2024

High-Performance RTL Simulation Workflow with Quartus and Active-HDL

Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will… High-Performance RTL Simulation Workflow with Quartus and Active-HDL

Aldec, March 21, 2024

High-Performance RTL Simulation Workflow with Vivado and Active-HDL

Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will… High-Performance RTL Simulation Workflow with Vivado and Active-HDL

Chips Alliance, November 9, 2023

CHIPS Alliance – FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development

IP share and reuse is fundamental for efficient chip design. But in order to do this efficiently we need tools and methods. On the software side, the concept of package managers is widely used to… CHIPS Alliance – FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development

Synopsys, October 19, 2023

High Reliability and Functional Safety Applications for FPGA

When designing any new system, safety and reliability are key factors in determining if a system is safe for real-world deployment and if there are sufficient contingency plans for worst case scenarios. This is no different… High Reliability and Functional Safety Applications for FPGA

Mirabilis, October 11, 2023

Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints

In this Webinar, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms onto the processors, logic and AI Engines resident in the… Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints

Doulos, September 20, 2023

Maximize Design Productivity using Vivado ML with SystemVerilog

Although SystemVerilog is perhaps most widely used in the context of hardware verification, it also contains many features directly relevant to FPGA hardware designers. We explore the features of SystemVerilog that are useful for RTL… Maximize Design Productivity using Vivado ML with SystemVerilog

FPGAworld 2023

FPGAworld Conference 2023 – Copenhagen

The FPGAworld Conference is an international forum for researchers, engineers, teachers, students, and hackers. It covers topics such as complex analog/digital/software FPGA SoC systems, FPGA/ASIC-based products, educational & industrial cases, and more. Registration for attendees… FPGAworld Conference 2023 – Copenhagen