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OSVVM

Aldec, August 22, 2024

Using OSVVM’s AXI4 Verification Components: Pt 1 Creating the AXI4 Testbench / Test Harness

European Session Abstract: This “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 1… Read More »Using OSVVM’s AXI4 Verification Components: Pt 1 Creating the AXI4 Testbench / Test Harness

Aldec, June 23, 2022

Advances in OSVVM’s Verification Data Structures

OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and… Read More »Advances in OSVVM’s Verification Data Structures

Aldec, May 26, 2022

Better FPGA Verification with VHDL: OSVVM – Leading Edge Verification for the VHDL Community

OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your… Read More »Better FPGA Verification with VHDL: OSVVM – Leading Edge Verification for the VHDL Community