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The Power of VHDL’s VHPI
April 27 @ 11:00 am - 12:00 pm PDT
The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers, if aware at all. Yet the simplest use of such interfaces opens up a whole world of possibilities in extending what is achievable in verifying logic IP and with the potential for logic and embedded software co-development.
The VHDL Procedural Interface (VHPI) is part of the IEEE Standard for VHDL Language Reference Manual. In this part 2 of the webinar series, we will introduce the VHDL VHPI and discuss the first steps of crossing from the logic domain to the software domain. We will show various working examples with OSVVM co-simulation, RISC-V ISS running in logic simulation and external programs connected via TCP/IP socket, sufficient to allow engineers to start creating their own solutions. The real-world examples will be demonstrated to show just what is possible with using these basic logic interface features that are already available, and well supported, in the Aldec simulation tools.
- VHDL VHPI
- OSVVM co-simulation VHPI interface
- OSVVM co-simulation environment
- Demo of RISC-V software ISS running in logic simulation
- Demo of external program connected via TCP/IP socket
- 45 min presentation/live demo
- 15 min Q&A