Designers increasingly use complex reset signaling architectures to meet high-performance, low-latency, and low-power requirements. Specifically, independent reset domains are created by complex reset sequences, reset… Read More »New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to… Read More »Comprehensive Static Verification for FPGA and ASIC RTL Designers
Today’s million gates integrated circuits (ICs) involve various intellectual properties (IPs) interfacing with each other through multiple asynchronous clock and reset domains. Ensuring all clocks… Read More »Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis
Low power is an increasingly critical requirement for all modern SoCs. Moreover, it is becoming more and more difficult with complex architectures being used in modern designs. This has made… Read More »Pre-empt Late-stage Low Power Issues using Predictive Analysis