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Synopsys, October 18, 2022

Improving Efficiency and Quality of Verification Environments with Automation

Bugs can be introduced at any stage in the hardware design development process and escape into tapeout if the verification environment is unqualified. Measuring and improving verification effectiveness to prevent bugs during functional verification is… Improving Efficiency and Quality of Verification Environments with Automation

Synopsys, June 9, 2022

5X Faster Equivalence Checking with Formality ML-driven DPX

Synopsys’ Fusion Compiler provides a broad spectrum of aggressive optimization techniques such as retiming, multibit banking and advanced data-path optimization that our designers want to take advantage of to achieve maximum PPA. Our expectation from… 5X Faster Equivalence Checking with Formality ML-driven DPX