CICC 2024
The IEEE Custom Integrated Circuits Conference is a premier conference devoted to IC development. The conference program is a blend of oral presentations, exhibits, panels… Read More »CICC 2024
Siemens
GSA European Executive Forum 2024
The GSA European Executive Forum, our flagship event in Europe, is BACK! Join us June 18th and 19th in Munich for the event of the… Read More »GSA European Executive Forum 2024
Deploying Solido Design Environment AI Workflows on AWS
Utilizing AWS cloud resources to accelerate variation-aware verification AI-powered Solido Design Environment provides SPICE-accurate variation-aware verification for 3, 4, 5, 6 and higher sigma targets,… Read More »Deploying Solido Design Environment AI Workflows on AWS
DFT for chiplets & 3D ICs using Tessent Multi-die
3D IC (2.5D/3D) designs are on the rise. Design for Test (DFT) for chiplets must be general purpose so they can be tested stand alone… Read More »DFT for chiplets & 3D ICs using Tessent Multi-die
osmosis Aerospace and Defense 2024 A Formal Verification Virtual Event
osmosis Aerospace and Defense (A&D) is about sharing the success in using formal techniques to address the demanding verification requirements and challenges of DO-254 compliant… Read More »osmosis Aerospace and Defense 2024 A Formal Verification Virtual Event
Guiding your aerospace electrical journey
Aerospace electrical/electronic (EE) design requires a delicate balance between innovative technology and uncompromising reliability. Meanwhile, the pressure to get products to market faster is growing… Read More »Guiding your aerospace electrical journey
DAC 2024
The premier event for the design and design automation of electronic chips to systems. Autonomous Systems Electronics content in modern autonomous systems (e.g., automotive, robotics, drones, etc.)… Read More »DAC 2024
Semicon West 2024
SEMICON West 2024 is North America’s premier conference and exhibition that gathers the incredibly diverse global electronics supply chain together to address the semiconductor ecosystem’s greatest opportunities… Read More »Semicon West 2024
Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim
Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can… Read More »Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim
Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and… Read More »Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification