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Siemens

Siemens, March 27, 2024

Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and… Read More »Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

Siemens, March 14, 2024

New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Designers increasingly use complex reset signaling architectures to meet high-performance, low-latency, and low-power requirements. Specifically, independent reset domains are created by complex reset sequences, reset… Read More »New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Siemens, February 27, 2024

From code to solution: tools and tactics for aerospace fault code troubleshooting

Join us in this insightful webinar as we delve into the world of aerospace and defense electrical fault code troubleshooting, unveiling the power of Capital™… Read More »From code to solution: tools and tactics for aerospace fault code troubleshooting