International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete… Read More »International Test Conference 2023
High-performance workloads demand on-package integration of heterogeneous processing units, on-package memory, and communication infrastructure to meet the demands of today’s data centers, autonomous vehicles, etc.… Read More »UCIe: On-Package Chiplet Innovation Opportunities
Watch as leaders from our government agencies, the Defense Industrial Base, and prestigious universities bring unique and indispensable perspectives on our domestic semiconductor industry, national… Read More »ERI 2.0 Summit
The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of… Read More »ESSDERC, ESSCIRC: 11-14 September
As traditional Moore’s law scaling approaches its physical limits, the industry is moving towards multi-die solutions for higher electronics system densities. Multi-die designs present one… Read More »Step-by-Step Guide for Your UCIe Design Verification
On behalf of the DVCon India 2023 steering committee, it is my pleasure to welcome you all to the 8th edition of the Design and… Read More »DVCon India 2023
RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA.… Read More »A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
As today’s designs are getting more complex, design constraints complexity also increases multifold. While ensuring design correctness typically gets a lot of attention including code… Read More »Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
224G SerDes designs are a reality and the path to 1.6T is clearer than ever. This webinar delves into the considerations, challenges and solutions designers need… Read More »Key MAC Considerations for the Road to 1.6T Ethernet Success
Continuously increasing semiconductor design sizes and complexity have resulted in increased test costs. Today’s competitive environment and critical market windows are pushing companies to adopt… Read More »Optimize Test QoR & TTM with AI-Driven Technology