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CXL DevCon 2024

April 30 @ 8:00 am - May 1 @ 5:00 pm PDT

CXL DevCon 2024

The CXL Consortium is looking forward to hosting the first Compute Express Link® (CXL®) DevCon from April 30 – May 1, 2024, in Santa Clara, California!

CXL DevCon is a unique opportunity for our Members to learn directly from CXL technology experts. Attendees will participate in CXL technical training, view available products and technology demonstrations, and network with industry peers.

Register for the event HERE.

If you are not currently a member of the CXL Consortium, learn about our membership benefits HERE and contact admin@computeexpresslink.org with any questions or for additional information.

 

CONFERENCE PROGRAM

DevCon 2024 Day 1 – Compliance & Implementation
Time Title Presenter(s)
8:00 – 9:00 Registration
9:00 – 9:15 Welcome Jim Pappas, Intel – CXL Chairman
9:15 – 9:45 Keynote – History of CXL Larrie Carr, Rambus – CXL President
9:45 – 10:15 CXL Specifications Overview Debendra Das Sharma, Intel – TTF Co-Chair
10:15 – 10:45 Coffee Break & Exhibit
10:45 – 11:30 Technical Spec Training (1.0/2.0) Mahesh Wagh, AMD – TTF Co-Chair
11:30 – 12:00 CXL Use Case – CXL Native Memory Bill Gervasi, Wolley
12:00 – 1:00 Lunch & Exhibit
1:00 – 1:20 Proving CXL scale-out and ROI in the data center Ira Weiny, Linux
1:20 – 1:40 CXL Software Ecosystem: The Software Stack for CXL Steve Scargall, MemVerge
1:40 – 2:00 Exploring Sunfish™: An Open-source Composable Disaggregated Infrastructure Framework Michael Aguilar, OpenFabrics Alliance – OFA Secretary
2:00 – 2:20 RAS for Resilient Data Centric Platforms using a CXL Memory Controller Sandeep Dattaprasad, Astera Labs
2:20 – 2:40 Member Implementation: CXL Memory Latency Measurement Tutorial Tam Do, Microchip
2:40 – 3:10 Break & Exhibit
3:10 – 3:30 Understanding the Need for Compliance Anil Godbole, Intel
3:30 – 3:50 Testing CXL links using Exercisers & Analyzers Yamini Shastry, Viavi
3:50 – 4:10 CXL Testing – Protocol Layers & Testing Examples Gordon Getty, Teledyne LeCroy
4:10 – 4:40 Focusing on the Future of CXL Compliance Nathan White, Intel – CWG Co-Chair
4:40 – 5:00 Day 1 Open Q&A CWG / TTF Panel
5:00 – 6:30 Networking Reception & Exhibit

 

DevCon 2024 Day 2 – Emerging & Future
Time Title Presenter(s)
8:00 – 8:30 Registration and Exhibit
8:30 – 9:30 Technical Spec Training (3.0/3.1) Rob Blankenship, Intel – PWG Co-Chair
9:30 – 10:00 Member Implementation: Streamlining CXL Adoption for Hyperscale Efficiency Nilesh Shah, ZeroPoint Technologies
10:00 – 10:30 Technical Training – Security: Integrity and Data Encryption (IDE) Trends and Verification Challenges in CXL Zongyao Wen, Synopsys
10:30 – 11:00 Coffee Break & Exhibit
11:00 – 11:20 Member Implementation Dr. Miryeong Kwon, Panmnesia
11:20 – 11:40 Member Implementation Geof Findley, Montage Technology
11:40 – 12:10 Member Implementation: Using a CXL 2.0 switch for CXL memory expansion, pooling and sharing Jianping (JP) Jiang, PhD, Xconn Technologies
12:10 – 12:30 Member Implementation: Building Composable and Disaggregated Systems of the Future with CXL 3.0 Raju Pudota, Cadence
12:30 – 1:30 Lunch & Exhibit
1:30 – 1:50 Member Implementation: Improving system memory bandwidth with CXL software interweaving Ravi Kiran Gummaluri, Micron
1:50 – 2:10 Member Implementation: Exploring system memory expansion and memory pooling/tiering Kapil Sethi, Samsung
2:10 -2:30 Member Implementation: Enabling CXL Memory Module, Exploring Memory Expansion Use Cases & Beyond Thomas Won Ha Choi, PhD, SK hynix
2:30 – 2:50 Member Implementation: Optical Applications of CXL David Kulansky, Alphawave Semi
2:50 – 3:30 Break & Exhibit
3:30 – 4:30 Fireside chat – open discussion + audience Q&A Leadership Panel
4:30 – 5:00 Closing comments and Call to Action Kurtis Bowman, AMD – MWG Co-Chair

Details

Start:
April 30 @ 8:00 am PDT
End:
May 1 @ 5:00 pm PDT
Event Categories:
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Event Tags:
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Website:
Event Website

Organizer

CXL
View Organizer Website

Venue

Santa Clara Marriott
2700 Mission College Blvd
Santa Clara, CA 95054 United States
+ Google Map

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