Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks… Read More »Running CDC Analysis with Xilinx Parameterized Macros
Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of… Read More »UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
Note, this is the tenth year of the present decade, so our next decade starts in 2021. Last week was my annual Merry Christmas gallery.