I’ll be moderating a panel session in the DAC Pavilion on Tuesday, June 15th starting at 4:30PM with real SPICE users from:
My first idea was to have EDA vendors on the panel, but then Dave Millman of Ciranova suggested that we use real SPICE users instead. I thought that was a brilliant idea.
What questions would you like to hear these SPICE users answer?
I’m thinking about the following for discussion:
We’re using the following SPICE tools:
- SPICE (name)
- FastSPICE (name)
- Analog FastSPICE (name)
- HDL + SPICE (name)
- HDL + FastSPICE (name)
We do circuit simulations using:
- Transient analysis
- Frequency analysis
- Monte Carlo analysis
- Sensitivity analysis
- IR drop
- Substrate noise
- Extracted parasitics
Our models are:
The capacity of our circuit simulations are:
- 10K transistors
- 100K transistors
- 1M transistors
- 10M transistors
- 100M transistors
- 1B transistors
Our IC technology is:
- Supplied by Foundry
- Our own fab
- 22nm, 28nm, 34nm, 40nm, 45nm, 65nm, 90nm, 180nm
What’s most important for our simulations are:
- Simulation speed, run times
- Mixed HDL and SPICE
The EDA vendors have been very good at supporting:
The EDA vendors really need to help us with:
We choose our present SPICE tools because:
Our SPICE tool flow is:
- Best in class point tools
- Integrated from one vendor
- Has our own internal tools
we, http://www.mos-ak.org, are ready to give an update on the spice/compact model Verilog-A coding and its standardization efforts.
please correct broken link “list of questions” pointing here from http://www10.edacafe.com/blogs/marketingeda/2010/03/17/what-is-new-with-spice/
I fixed that broken link, thanks for pointing it out.
Can we have a public update on the SPICE/Compact Model here?
I think it would be of good value to our readers.