Ed Cheng, CEO at Gradient Design Automation recently spoke with me about his unique company focused on thermal analysis of IC designs. I first met Ed at Silicon Compilers in 1986, plus we both worked at Intel before that.
Q: Who would use your tools?
A: Our end users are chip designers at the gate and transistor levels.
Q: What does your tool do?
A: It’s a simulator for temperature on ICs. As a chip operates it dissipates power which then heats the IC which is non-uniform across the die. It can pin point the exact XY location of your heat issues.
Q: What does the simulator take into account?
A: It understands the thickness of the chip plus other foundry-specific details to ensure accuracy.
Q: When I get a PDK from the foundry does it include the info to run your tools?
A: No, the PDK doesn’t have our thermal info yet. The fabs have provided that data to us, and we provide it to users.
Q: Which power analysis tools do you integrate with?
A: All of the major EDA vendors: Cadence, Synopsys, Mentor, Magma
Q: What types of thermal analysis are there?
A: Two types: steady state and transient thermal analysis. The transient is most accurate.
Q: How do I know that the thermal results are correct?
A: Customers have run test chips to correlate actual results with simulated.
Q: What OS do you support?
A: Linux mostly.
Q: What capacity does this tool have?
A: We have customers running billion transistor designs with our tools. You can break up larger designs into pieces to speed up simulations too.
Q: What types of IC designs really need thermal analysis today?
A: High precision analog, for example a differential amplifier must have balanced inputs to perform correctly and the current sources to the differential pairs require precise matching. Any thermal difference in these sensitive circuits will produce incorrect results.
Q: Do reliability engineers run this tool?
A: Yes, both reliability and design engineers run this tool.
Q: What is the methodology to use the tool?
Q: Is thermal analysis similar to other EDA tools?
A: Yes, consider the analogies with timing analysis. With thermal analysis we also have aggressors and victims, where a victim net or MOS device is sensitive to a temperature change caused by a nearby aggressor device. Power management chips really need this kind of analysis.
Q: How is thermal analysis related to Electromigration?
A: EM failure is caused by high temperatures, so we can show you where to find your thermal issues before tapeout to save you spins and money.
Q: Can your tools analyze stacked dies?
A: Yes, with stacking we see an even greater need to analyze the thermal results to ensure safe operation.
Q: What about TSV (thru Silicon Vias)?
A: Yes, we can analyze that structure too. Consumer devices like cell phones are using thinner dies and stacked dies to keep sizes small.