I’ve been watching for several years now and the claims of Ciranova to automate analog layout are certainly coming true. Today they proudly talked about CSR using their Helix and PyCells tools for some very challenging analog IC designs in wireless products:
- Echo/Noise Suppression
If you feel a bit burdened to start an evaluation of Ciranova tools then how about sending your existing analog design over to them to see how they can automate the layout process? The new program is called Rapid Analog and the pricing starts at free for designs targeted for TSMC or $9K for other foundries.
In the olden days we talked about how many transistors per man-day you could layout with one team for circuit design, and another team doing IC layout. Using the approach from Ciranova any circuit designer can now get to layout by using automated tools. Maybe this is less job security for layout designers but an accelerator for the circuit designers who now have layout control in much less time.
If I were to compare IC layout to writing books, then hand-crafted IC layout is like using calligraphy while Ciranova is like using a word processor with spell checking and grammar checking. I’ll take automation for my IC layouts and then enjoy the early to market rewards.
My sources in CSR tells me that the design engineers are not very happy with being pushed to use Ciranova. In any case, the design management who promoted Ciranova is mostly gone.
Thanks for the update. I still see Ciranova as a rising star in EDA, especially in light of the recent investment by Intel, http://www.chipdesignmag.com/payne/2010/09/14/ciranova-receives-intel-funding/