Amr Bayoumi, Ph.D.  (Chief Technical Adviser) from New Systems Research spoke with me via Skype on Friday. We had a DAC meeting scheduled but I made a mistake about the meeting location and missed it.

The last company to use a GPU to accelerate SPICE results was Nascentric, and now they’re out of business. They only reported a 4X speedup using a GPU.

Co-founder Yasser Hanafy, earned his PhD at Duke and did work on parallel SPICE (4 CPUs).

The SPICE algorithm spends most of it’s time doing matrix operations, so how do you make it parallel?

They started with three Alpha customers and tuned the SW last year. Now they are in the Beta phase.

Competitors Magma and Cadence have figured out how to use multi-cores to speed up SPICE simulation results.

Speed ups seen so far: Device modeling, matrix solving – 70x to 100x on device modeling (GPU plus multi-core). Matrix times are 20 to 30X faster with a GPU than using a single core.

Competitive advantages include: work as engines, so this technology can be re-used with any SPICE circuit simulator. Low overhead company, based in Cairo, Egypt. Have research grants. ATI (co-written article in IEEE in December) work closely with them.

What is the SPICE simulation capacity ?
A: Able to SPICE 1M elements.

What is your Business Model?
A: Want to sell this IP to Cadence, Mentor, Magma, etc.

How many cores can I use with your SPICE tool?
A: 8 processor maximum

What designs work best with your SPICE?
A: Post-layout netlists, large number of RC elements.

What simulation models do you support?
A: BSIM3 or BSIM4 models

Do you exploit netlist hierarchy?
A: Flat simulation, not hierarchical.

When do you expect to be at production release?
A: Production by March 2010.

This GPU acceleration of SPICE looks very promising so I wonder how long it will be before one of the bigger EDA companies buys this technology.