If your next design has 100 million gates then what tools are you going to use for logic synthesis?
Until today you would be faced with breaking up your design into blocks and then stitching them together, hoping that your partitioning didn’t miss any critical paths that cross block boundaries.
Oasys is the newest logic synthesis vendor to claim 100 million gate capacity with their new RealTime Designer tool. Not only capacity but they are claiming some incredible run-time inprovements too. Don’t miss this company at DAC if you’re on the bleeding edge of gate count.
Renesas in Japan is the first named customer of the tool.
Speaking of Japan, it seems that Cadence wanted to counter the Oasys announcement last week by releasing an endorsement from STARC about their logic synthesis capacity of 20+million gates.
Competition is wonderful in EDA and I look forward to seeing who wins this highest-end logic synthesis battle.
Finally, I admire when a company like Oasys simply tells us the pricing for their new tool. I don’t have to find an Account Manager, get qualified and then finally learn about the $395K annual pricing.
How long before Synopsys catches up to this capacity and speed?
Design Compiler is now 20 years old. At some point starting over with a blank sheet of paper, as Oasys appears to have done, allows you to revisit a number of architectural decisions that may have become increasingly less appropriate for today’s designs.
Oasys has been at it for four years and has several customers who are endorsing them. I suspect if everything that they have said is true, and there is no reason to doubt it given the team’s prior EDA experience, then they may take significant share from Synopsys unless Synopsys is prepared to also start from scratch sooner rather than later.
One of the most interesting things about the announcement was the lack of any VC’s on the board. They seem to have taken a lot of “smart money” from EDA Angels which may also be patient money. If that’s the case then they won’t face near term pressure to sell out and may actually trigger a re-alignment in the industry leaders.
Sean, good points. The Oasys approach of Place First does sound unique, so let’s see how it gets accepted by the bleeding-edge chip design teams out there.