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An Efficient Method to Perform Functional ECO Using Formality ECO
May 12, 2022 @ 10:00 am - 11:00 am PDT
During complex IP development, effort and time taken to perform a functional ECO is very high. It involves analysis and understanding of huge combinational and sequential blocks, and usually runs into multiple iterations if done manually. For example: the physical netlist multibit register mapping could be different and Synopsys IC Compiler II would not be able to perform the ECO straight away on the given ECO’d synthesized netlist, even though the RTL to synthesis equivalence is established using Synopsys Formality. In addition, using a manual approach to implement an ECO can be error prone and takes multiple Formal equivalence iterations to validate.
In this Synopsys webinar, presenters from Samsung and Synopsys will demonstrate an automated method that can be used to do a functional ECO for a fairly complex design with an ECO that may add sequential and combinational logics. Starting from an edited RTL to a patch implemented on an IC Compiler II PD netlist, the flow is completely automated and doesn’t need any manual intervention. This method significantly reduces the turnaround time to generate the functional ECO netlist. The only requirement to start is to have original RTL passing through Formality with the original netlist and have the new ECO’d RTL. This flow makes use of Synopsys Formality ECO.
Listed below are the industry leaders scheduled to speak.
Praveen S Bharadwaj
Associate Technical Director
Praveen S Bharadwaj has been an Associate Technical Director at Samsung Semiconductor India Research (SSIR) since 2017. He leads the SerDes RX projects which involve all front end activities including equivalence checks and synthesis for multiple SerDes IPs in multiple process nodes. Praveen received his Master’s from North Carolina State University and has 12 years of IP design experience.
Product Marketing Manager
Avinash Palepu is the Product Marketing Manager for Formality and Formality ECO products. Starting with Intel as a Design Engineer, he has held various design, AE management and Product Marketing roles in the semiconductor design and EDA industries. Avinash holds a Master’s degree in EE from Arizona State University and a Bachelor’s degree from Osmania University.