CadenceCONNECT: The Race Is On!

Event Overview

Date: Monday, November 13, 2023

Time: 8:30am – 4:00pm, followed by an exclusive networking event

Location: Cadence Headquarters, San Jose, CA

There is an unprecedented demand for advanced-node chip design that pushes beyond traditional boundaries. Computing power, security, reliability, and other multifaceted requirements have surpassed the basic performance, power consumption, and area constraints of traditional chip design. The race is on to enable traditional automotive companies to enter the new field of automotive electronic chips quickly, and to improve the performance of established automotive chips to deliver higher and higher computing capabilities while meeting safety and reliability requirements.

Join Cadence on November 13, at Cadence headquarters in San Jose, as we present a new generation of automotive electronics chip design full-flow solutions. Learn about the most recent advancements in the field of automotive chips, including upcoming technology trends and innovations, such as autonomous driving to electric vehicles, functional safety, reliability of automotive semiconductors, and more.

Who Should Attend

CAE professionals with a background in electrical engineering, fluid dynamics, engineering directors and managers, and engineering team members who work in automotive electronics (SoC) design, as well as academics and researchers from relevant fields are welcome.

What You Will Learn

• Design IP for Automotive SoC Design
• 3D-IC Design and Interconnect IP Solution for Chiplet-Based Design
• Configurable Multi-Core DSP and AI Platform for Automotive Applications
• FMEDA-Driven Safety Analysis and Verification
• Safety-Aware Implementation
• Analog/Mixed-Signal Safety Verification
• System Design and Analysis (EMI, EMC, Electrothermal)
• Automotive CFD Solutions (Aerodynamics, Aeroacoustics, HVAC, Turbo/Pumps, ​
  Thermal Management)