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Comprehensive CXL 3.0 Verification Solution for High-Bandwidth and Low-Latency Connectivity
February 21 @ 9:00 am - 10:00 am PST
Join us for a deep dive into the most comprehensive CXL Verification IP solution available in the market that targets 1.1, 2.0 and 3.0, Siemens Avery CXL Verification IP.
Compute Express Link (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices. CXL 3.0 provides a range of advanced features and benefits including doubling bandwidth with the same latency.
To rapidly meet the growing needs for the CXL datacenter ecosystem, developers of server processors, managed DRAM and storage class memory (SCM) buffers, switch/retimer, and IP companies need a comprehensive CXL verification solution that enables rapid and thorough system interoperability, validation and performance benchmarking of systems targeting the full range of versions of the standard, including 1.1, 2.0 and 3.0.
What You Will Learn:
- Considerations for exhaustive verification of the CXL interconnect
- Unique features in Siemens Avery CXL Verification IP, including, capabilities for scalability and resource utilization, realistic traffic arbitration and unified user application data class for PCIe and CXL traffic
- How Siemens Avery CXL Validation Suite enables hardware and software development teams to start system integration and validation extremely early
Who Should Attend?
- Design and verification engineers
- Firmware engineers and architects working on CXL projects
The session will include a demonstration of the CXL Validation Suite, followed by Q&A with the presenters.
Speakers:
Chris Browy is Senior Director of Siemens VIP Product Line. He came to Siemens recently through the acquisition of Avery Design Systems where he was co-founder and served as VP Sales/Marketing for close to 25 years. From 1989 to 1998, Chris held various positions at Cadence Design Systems including Director of ASIC Design Services, Director of Top-down IC Design Practice, and product marketing manager for synthesis, timing analysis, and test products. Prior to Cadence, Chris held numerous other positions in EDA applications engineering and ASIC design involving large-scale ATM switching systems, Non-linear digital video editing systems, and massively parallel multiprocessors and super minicomputers. Chris received a B.S.E.E. from Rensselaer Polytechnic Institute in 1984 and resides in New Hampshire.
Tzi Yang Shao is the lead developer at Siemens in the VICS Product Line. His association with Siemens commenced with the acquisition of Avery Design Systems, and he has dedicated six years to the company. Tzi Yang actively contributes to CXLCV development, demonstrating his proficiency in QEMU and various protocols. In 2017, he earned an MPhil in Technology Leadership and Entrepreneurship from the Hong Kong University of Science and Technology, complementing his background in Electronic Engineering.