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Connect Your System Architecture Design and Implementation

February 23 @ 8:00 am - 9:00 am PST

Cadence, February 23, 2022

Join Cadence Training and Senior Application Engineer Dave Palumbo for this free technical Training Webinar.

The disconnect between system architecture design and implementation makes creating a system that meets cost, performance, and form factor requirements challenging. Hardware designers need tools that help them engineer systems to meet the goals of their end products within the time-to-launch window.

Cadence® Allegro® System Capture is a scalable, easy-to-use solution for fast system design intent creation that allows the high-level system architecture and functional diagram to stay connected to the detailed implementation of each board. Allegro System Capture provides an intuitive, easy-to-use environment for hardware designers and architects to engineer a system that is correct by construction. This enables partitioning a system into multiple boards and ensures that system assembly and connectivity are current from the beginning and throughout the design process. Allegro System Capture also enables the high-level functional and architectural description of the multi-board system to stay in sync with the detailed implementation of each of the boards in the system.

In this webinar, you’ll learn about:

  • Constraint Management: Define limitations upfront to shorten design cycles and reduce errors
  • Front-to-Back Integration: Easily transfer your design to begin layout while maintaining a link to your schematic in case of mid-cycle changes
  • Cross Probe: Quickly find components on the board and ensure accuracy and completeness
  • Schematic-Driven Placement: Specify component association between an active device and associated decoupling capacitors, as well as maximum distance between the decoupling capacitors and the power/ground pins on the active component
  • Design Reuse and Variants: Reuse existing proven design IP to get your designs done faster and ensure functionality
  • Schematic Validation: A set of checks to prevent common errors in creating schematics

Date and Time
Wednesday, February 23
08:00 PST / 11:00 EST / 16:00 GMT / 17:00 CET / 18:00 IST/ 21:30 IST (India)

To register for the “Connect Your System Architecture Design and Implementation”webinar, use the REGISTER button below and sign in with your Cadence Support account (email ID and password) to login to the Learning and Support System. Then select “Enroll” to register for the session. Once registered, you’ll receive a confirmation email containing all login details.

If you don’t have a Cadence Support account, go to Registration Help or Register Now, and complete the requested information.

Details

Date:
February 23
Time:
8:00 am - 9:00 am PST
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Organizer

Cadence
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