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Customers Discuss Their Real World Use of High-Level Synthesis

June 8, 2022 @ 8:00 am - June 9, 2022 @ 12:00 pm PDT

Siemens EDA, June 8-9, 2022

The focus of this seminar is to have real-world customers present their successes using Catapult High-Level Synthesis (HLS) in markets such as Automotive, 5G/Communications, Video/Imaging, AI/ML, and MEMs Sensors. The companies who will be presenting are:

  • Google (Video/Imaging)
  • NASA-JPL (Video/Imaging)
  • NVIDIA (Video/Imaging)
  • NVIDIA Research (AI/ML)
  • NXP Semiconductors (Automotive)
  • STMicroelectronics (MEMS Sensors)
  • Viosoft (5G/Communications)

In this seminar, leading experts will present how they have successfully deployed HLS in production design flows.

Day 1 Sessions
June 8th 8:00AM PST-11:40AM PST


Day 2 Sessions
June 9th 8:00AM PST – 11:00AM PST

8:15 AM (40 min) – NVIDIA: Applying Catapult HLS design and Verification to NVIDIA’s Large Scale Video Codecs: Benefits and Challenges

8:45 AM (40 min) – STMicroelectronics: High-Level Synthesis in Analog Native Products Upward Trend

9:30 AM (40 min) – NASA-JPL: Pros and Cons of a C++ Flow vs. a SystemC Flow for the Harris Corner Detector
10:10 AM (40 min) – Viosoft: Functional Exploration and Offloading of 5G Physical Layer Protocol Stack
10:50 AM (10 min) – Closing Session
Stuart Clubb
Technical Product Management Director
Siemens EDA

Stuart is responsible for Catapult HLS Synthesis and Verification Solutions since July 2017. Prior to this role, Stuart had been successfully managing the North American FAE team for Mentor/Siemens and Calypto Design Systems and was key to the growth achieved for the CSD products after the Calypto acquisition. Moving from the UK in 2001 to work at Mentor Graphics, Stuart held the position of Technical Marketing Engineer, initially on the Precision RTL synthesis product for 6 years and later on Catapult for 5 years. He has held various engineering and application engineering roles ASIC and FPGA RTL hardware design and verification. Stuart graduated from Brunel University, London, with a Bachelors of Science.

Michael Fingeroff
HLS Technologist
Siemens EDA

Michael Fingeroff has worked as an HLS Technologist for the Catapult High-Level Synthesis Platform at Siemens Digital Industries Software since 2002. His areas of interest include Machine Learning, DSP, and high-performance video hardware. Prior to working for Siemens Digital Industries Software, he worked as a hardware design engineer developing real-time broadband video systems. Mike Fingeroff received both his bachelor’s and master’s degrees in electrical engineering from Temple University in 1990 and 1995 respectively.

Reinhold Schmidt
Digital Designer
NXP Semiconductors

My main focus is digital signal processing, where I work on digital baseband processing systems for RF communication devices.

I used to work on decimation chains, narrowband interference cancellation, analog mismatch compensation. Now I am focusing more on subsystem level meaning the complete baseband design of ultra wideband radios.

Aki Kuusela
Senior Engineering Manager, Consumer Hardware

Aki Kuusela is an Engineering Manager at Google’s Devices & Services unit. He has an M.S. in electrical engineering from University of Oulu, Finland, and has worked on video compression and various hardware accelerators for more than 20 years. He joined Google in 2010 and has participated in the development of the open video formats VP9, AV1 and AV2 within the Alliance for Open Media. He is a strong supporter of high-level synthesis design flows, having taped out his first HLS design in 2014. At Google he has worked on both data center and consumer chips, including the VCU ASIC and the Tensor SoC.

Nathaniel Pinckney
Senior Research Scientist
NVIDIA Research

Nate Pinckney received his B.S. degree in engineering from Harvey Mudd College in 2008, and his Ph.D. in electrical engineering from the University of Michigan in 2015. He has authored or coauthored over 40 publications in the areas of high-level synthesis methodologies, low-power VLSI design, and cryptographic accelerators. In 2015, he joined NVIDIA in Austin, TX.

Hai Lin
Senior ASIC Design Engineer

Graduated as EE master from Shanghai JiaoTong University at 2008 and joined NVIDIA Shanghai R&D site as ASIC verification leader for GPU NOC unit. Started to work for Shanghai video design team since 2016 and lead video jpg engine developing, started to develop HLS design flow since 2018 and lead HLS design methodology team for NVIDIA Shanghai R&D site.

Sandro Dalle Feste
Electronic R&D Senior Director

Sandro Dalle Feste graduated from Politecnico of Milan during 1992 with a degree in Electronic Engineering. He joined STMicroelectronics in 1993 working on Sigma Delta Converters and Digital Signal Processing on CMOS processes. He extended his activity to wide band and high-speed circuits and converters at the end of 90’ becoming a Design Manager for High Speed IPs mainly for communication systems. In this period, he was responsible for the design of various products designed in CMOS and BICMOS process. He then moved to Audio products developing full family of digital power amps for Home Systems and TV application, approaching in this context BCD technologies. Starting from 2010 as Product Development Manager, he took care about system platform developments in cooperation with strategic Customers, including ASICS and MEMS devices and spacing from MEMS sensors to actuators. In this career, he was author of technical publications and patents. He is now Electronic R&D Senior Director within Analog and MEMS Group with the responsibility for strategic and innovative programs. He is a member of the scientific technical committee for JRC, a joint research centre between STMicroelectronics and Politecnico di Milano.

Ashot Hambardzumyan
FPGA Engineer

Ashot received his B.S in Computer Engineering from California Polytechnic University of Pomona and his M.S in Computer Science from Georgia Institute of Technology. He is the principle investigator for High Level Synthesis for Jet Propulsion Laboratory’s Autonomous Systems division. His experience includes FPGA verification lead for Mars Ingenuity Helicopter and FPGA designer on Entry Descent and Landing vision accelerator. Currently, he is in charge of computer vision FPGA accelerators for JPL’s Mars Sample Return project.

Hieu Tran


June 8, 2022 @ 8:00 am PDT
June 9, 2022 @ 12:00 pm PDT
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Siemens EDA
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