Debugging Features of UVM

A UVM testbench is a large and complex piece of software. Like any other large and complex piece of software, a verification environment written using UVM will require debugging at some stage. There are various debugging features built into UVM to help with this.

In this one-hour webinar, Doulos Senior Member Technical Staff Doug Smith explores the various features in UVM to help you debug your UVM environment, test cases, and design under test.

Topics include:

• Debugging the Testbench
• Debugging Stimulus
• Debugging the Design

At the end of the webinar, we will also look at an example of the tool support features for debugging UVM using the Cadence Xcelium Logic Simulator.