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IP-SoC Conference 2022

November 30 @ 8:00 am - December 1 @ 5:00 pm CET

IP-SOC 2022

IP-SoC 2022 will be the 25th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems.

The event is the annual opportunity for IP providers and IP consumers to share information about technology trends, innovative IP SoC products, Breaking IP/SoC News, Market evolution and more.

The Grenoble event is a special event as it is also the annual IP Think Tank meeting where high level executives, market analyzer and technical experts in all the design track from Foundry, technology, design methodology, EDA tools share their vision about the future of the IP concept. It will be the right time to analyze the fast evolution and consolidation in the IP market and IP business.

And over all you cannot miss The wine Tasting Party and special banquet for D&R 25th Anniversary !!

Exhibition tables and “discussion panels” will favor vendor and customer meetings.

Any question? Please contact us

Tentative Program

Day 1 – November 30th, 2022

Welcome

  • After 25 years what’s new, Design And Reuse
  • The processor revolution is brewing – it won’t be like the past 25 years!, Codasip GmbH
  • Sustainability of the electronic industry : A major challenge and a mine of innovation, STMicroelectronics

SOI the “European Green Touch”

  • CHIPS ACT: How Europe wakes-up, Soitec
  • FDSOI the EU technology for a green transition, Soitec
  • OCEAN12 IP Factory: From Research to Silicon, Fraunhofer-Gesellschaft
  • BEYOND5 – Low power 5G access point, ASYGN
  • BEYOND5 – Car Interior Radar for Advanced Life-Signs Detection, Silicon Radar GmbH

Automotive Solution

  • Securing next generation semiconductors for Automotive, Rambus, Inc.
  • CAN ALL – secure & comprehensive solution (not only) for automotive, Digital Core Design
  • Automotive-Grade IP for Next-Generation Zonal Architectures, Synopsys, Inc.

Video & Imaging & Artificial Intelligence

  • Leveraging MIPI DSI-2 & MIPI CSI-2 Low-Power Display and Camera FPGA-based Subsystems, Mixel, Inc.
  • Ultra-compact image compression IP core for saving on chip SRAM, Lemur-Imaging Ltd.
  • nearbAI: scalable neural network inference for ASICs in XR devices, easics NV

RISC-V

  • RISC-V and Functional Safety, Andes Technology Corp.
  • RISC-V in Space, CAES Gaisler
  • Increasing commercial adoption of RISC-V, Cadence Design Systems, Inc.
  • RISC-V processor IP product line, CloudBEAR

Security Solution

  • Secure your designs with world-class security IP, Crypto Quantique
  • RAID System Based on Reed Solomon Code Galois Field, Secantec, Inc.
  • Post-Quantum Cryptography: Theory to Accelerated Practice, Synopsys, Inc.
  • Building a Root of Trust with SRAM PUF and tRoot HSM, Intrinsic ID
  • The importance of security lifecycle management, Secure-IC

Day 2 – December 1st, 2022

Chiplet and Die-to-Die Interface

  • Chiplet and Die-to-Die Interface Interoperability – how to accelerate path to a real Open Ecosystem, Alphawave IP, Inc.
  • Strength of UCIe for Multi-Die Systems, Synopsys, Inc.

Low Power / Low Energy Design

  • Democratizing Energy Friendly Ambient Computing, Dolphin Design
  • Lowering the power consumption of voice-controlled IoT devices, Phonemic

Memory and Analog IP

  • How Embedded Non-Volatile Memory IP Can be a Differentiator, Weebit Nano
  • Analog IP, the way you want it, Agile Analog
  • All you need is an Electrical Rule Checker !, Aniah
  • FDSOI High speed, low power hybrid ADC’s for Communications, AI, and Automotive applications, Alphacore, Inc.

Ethernet IP

  • Deterministic transmission of time critical information with TSN Ethernet (Time Sensitive Network), Comcores
  • Addressing performance challenges of TCP/IP stack implementations, CAST, Inc.

IP based SoC Design

  • Unified methodology for SoC design assembly including logic, power and timing constraints, Defacto Technologies
  • Tackling ROIC SoC Design Reuse challenges with AMALIA platform, Thalia Design Automation
  • Essential IP for the Enablement of Silicon Lifecycle Management, Synopsys, Inc.
  • Programmable logic for ASIC/SoC without pain, Menta

And more to come…

Click here to register >>

Venue

Hotel Europole
29 rue Pierre-Sémard
Grenoble, France
+ Google Map

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