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FPGA Design/Verification: Code, Functional and Specification Coverage

May 19 @ 11:00 am - 12:00 pm PDT

Aldec, May 19, 2022

Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you have no randomization at all. This is a great method for ensuring that you are in fact checking the right things in your testbench.  Unfortunately, not many designers are applying functional coverage, and maybe part of the reason for that is the complexity surrounding previous solutions to this functionality. This presentation will show you how it works and how easy it is to get started with this new functionality in UVVM.

The presentation will also explain and show the usage of Specification Coverage aka Requirement Coverage, which is a feature to track that all your specification requirements have been covered.
Many of us are already familiar with Code Coverage since it’s very easy to use, but some important issues will be presented.

 

Agenda:

  • Code Coverage briefly explained and discussed
  • Why and When do we need Functional Coverage?
  • How do we apply and use Functional Coverage?
  • Variants of Functional Coverage
  • What is Specification Coverage and Why do we need it
  • How do we apply and use Specification Coverage?
  • Conclusion
  • Q&A

Webinar Duration: 

  • 45 min presentation/live demo 
  • 15 min Q&A

Presenter

Bio:

Espen Tallaksen, CEO of EmLogic
Espen is also the author and architect of UVVM and founder of previous Bitvis.
He has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.

Sunil

 

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